Scan circuit with bootstrap drive

ABSTRACT

There is provided a scan circuit in which a plurality of unit circuits are connected and scan pulses are sequentially output from the unit circuits in response to drive pulses. In this circuit, the potential at an output terminal of the unit circuit is raised by one drive pulse. The potential at the output terminal is further increased by use of the bootstrap effect by the other drive pulse, thereby forming a scan pulse.

This application is a division of application Ser. No. 196,479 filed May20, 1988 now U.S. Pat. No. 4,922,138.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a scan circuit in which a plurality ofunit circuits are connected and scan pulses are sequentially output fromthe unit circuits in response to drive pulses.

2. Related Background Art

FIG. 1 is a schematic circuit diagram of a drive section in a solidstate image pickup apparatus using a conventional scan circuit.

In the diagram, respective output terminals of a scan circuit 401 areconnected to horizontal lines HDL₁, HDL₂, and HDL₃, and to horizontallines HDL₃, HDL₄, HDL₅, . . . through transistors Qy₁ to Qy₄.

A signal F₁ to select odd number fields is input to gate electrodes ofthe transistors Qy₁ and Qy₂. A signal F₂ to select even number fields isinput to gate electrodes of the transistors Qy₃ and Qy₄ Namely, thetransistors Qy₁ to Qy₄ constitute an interlacing circuit.

When the signal F₁ is input, scan pulses Oy₁, Oy₂, . . . aresequentially output to the horizontal lines HDL₁ and HDL₂, horizontallines HDL₃, and HDL₄, . . . through the transistors Qy₁ and Qy₂.

On the other hand, when the signal F₂ is input, the scan pulses Qy₁,Qy₂, . . . are sequentially output to the horizontal lines HDL₂ andHDL₃, the HDL₄ and HDL₅, . . . through the transistors Qy₃ and Qy₄.

However, in the foregoing image pickup apparatus using the conventionalscan circuit, the signals F and F₂ are transferred to the horizontallines HDL through the transistors Qy₁ and Qy₂ and the transistors Qy₃and Qy₄ of the interlacing circuit. Therefore, there are problems suchthat a voltage drop due to a threshold value voltage Vth of thetransistor Qy occurs and the dynamic range is narrowed, so that thepicture quality deteriorates.

To solve this problem, in Japanese Patent Gazette No. 61-61586, avertical buffer circuit to compensate a voltage level of the scan pulseOy is provided. However, since the buffer circuit is separatelyprovided, the number of elements constituting the vertical scan circuitincreases and also the buffer circuit has a bootstrap capacitance. Thus,there is a problem such that it is difficult to reduce the area of theelements.

On the other hand, since two horizontal lines are simultaneously driven,the conventional drive circuit cannot be used in the image pickupdevices in which a signal is readout by every one vertical line. Namely,the conventional constitution has problems such that there is alimitation in driving manner and this constitution can be applied toonly the limited driving method.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a scan circuit whichcan output scan pulses of an enough high level without providing anyspecial circuit to compensate a voltage level of the scan pulses.

According to one embodiment of the present invention, there is provideda scan circuit in which a plurality of unit circuits are connected andscan pulses are sequentially output from the unit circuits in responseto drive pulses, wherein a potential at an output terminal of the unitcircuit is raised by one drive pulse and the potential at the outputterminal is further increased by use of the bootstrap effect by anotherdrive pulse, thereby forming the scan pulses.

In this manner, since the scan pulse at a high voltage can be output byuse of the bootstrap effect, the voltage drop by the interlacing circuitor the like can be sufficiently compensated. Any special compensatingcircuit like the conventional circuit is unnecessary. The constitutionof the circuit can be simplified and the area of the devices can beeasily reduced.

On the other hand, according to another embodiment of the invention,there is provided a drive circuit of a solid state image pickupapparatus for supplying a drive signal to a plurality of drive lines todrive image pickup elements, wherein a switching means are provided foreach output of the scan circuit and the drive signals can be supplied todesired drive lines through the switching means, and the drive signalscan be supplied to the drive lines in a desired mode by a desiredcombination of the scan output of the scan circuit and the drivesignals.

With this constitution, even when a plurality of drive lines arescanned, each line can be independently driven and various kinds ofdriving modes such as interlacing scan, non-interlacing scan, and thelike of a plurality of lines can be easily realized.

The above and other objects and features of the present invention willbecome apparent from the following detailed description and the appendedclaims with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic circuit diagram of a drive section in a solidstate image pickup apparatus using a conventional scan circuit;

FIG. 2A is a partial circuit diagram in the first embodiment of a scancircuit according to the present invention;

FIG. 2B is a voltage waveform diagram in the respective sections forexplaining the operation of the embodiment;

FIG. 3 is a partial circuit diagram of the second embodiment of theinvention;

FIG. 4 is a voltage waveform diagram for explaining the operation of thecircuit in FIG. 3;

FIG. 5 is a schematic circuit diagram of a drive section using a scancircuit of the embodiment;

FIG. 6 is a timing chart for explaining the operation of the drivesection of FIG. 5;

FIG. 7 is a schematic circuit diagram of another example of a drivesection using the scan circuit of the embodiment;

FIG. 8 is a timing chart for explaining the operation of the drivesection of FIG. 7;

FIG. 9 is a schematic cross sectional view showing an example of aphotoelectric converting cell which is used in a solid state imagepickup apparatus;

FIG. 10A is an equivalent circuit diagram of the photoelectricconverting cell;

FIG. 10B is a voltage waveform diagram for explaining the operation ofthe circuit of FIG. 10A;

FIG. 11 is a schematic circuit diagram of the image pickup apparatususing the photoelectric converting cell; and

FIG. 12 is a timing chart for schematically explaining the operation ofthe image pickup apparatus of FIG. 11.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

An embodiment of the present invention will be described in detailhereinbelow with reference to the drawings.

FIG. 2A is a partial circuit diagram of the first embodiment of a scancircuit according to the invention. FIG. 2B is a voltage waveformdiagram in the respective sections for explaining the operation of theembodiment.

In this embodiment, n unit circuits are connected and scan pulses φ_(l)to φ_(n) are sequentially output from the unit circuits. It is assumedthat a potential of each section in FIG. 2A is expressed like V(i) usingthe number (i) added to each section.

In the diagrams, in the unit circuit at the first stage, when a pulseφ_(v1) rises after a pulse P_(s) was applied, a transistor M₁ is madeconductive and the potential V(4) rises. Since the potential V(4) is thegate potential of a transistor M₂, the transistor M₂ shows a conductancecorresponding to the potential V(4).

Subsequently, when the pulse φ_(v1) falls and a pulse φ_(v2) rises, thepotential V(5) increases through the transistor M₂. The increase in thepotential V(5) is fed back to a gate of the transistor M₂ via acapacitor C₁, thereby increasing the potential V(4) due to the bootstrapeffect. The increase in the potential V(4) acts so as to raise aconductance of the transistor M₂. Therefore, the pulse φ_(v2) passes,while a voltage drop hardly occurs due to the transistor Mhd 2. Thispulse is transmitted through a transistor M₃, thereby increasing thepotential V(6).

Since the potential V(6) is the gate potential of a transistor M₆, aconductance of the transistor M₆ rises in correspondence to thepotential V(6).

When the pulse φ_(v1) subsequently rises, the potential V(7) increasesthrough the transistor M₆. The potential V(6) further rises due to thebootstrap effect owing to the increase in the potential V(7). Since theincrease in the potential V(6) acts so as to enhance the conductance ofthe transistor M₆, the pulse φ_(v1) allows the potential V(8) to beraised through the transistors M₆ and M₇ (refer to FIG. 2B). Therefore,a transistor M₁₀ exhibits the conductance corresponding to the gatepotential V(8).

Next, when the pulse φ_(v2) rises, the transistor M₈ is turned on andthe potential V(7) is reset to the earth potential and the transistor M₇is turned off. Thus, the portion of the potential V(8) is set into thefloating state.

At the same time, since the pulse φ_(v2) rises, the potential V(9) risesthrough the transistor M₁₀. The increases in the potential V(9) furtherincreases the potential V(8) by the bootstrap effect.

If such a change in the potential V(8) is used as a scan pulse φhd 1, ascan pulse at a high voltage can be obtained.

Next, the potential V(8) is reset by the pulse φ_(v1) and at the sametime, the potential V(12) rises and, further, increases by thesubsequent pulse φ_(v2). The potential V(12) is used as a scan pulse φ₂.In a manner similar to the above, scan pulses φ₃ to φ_(n) at a highvoltage level are successively output synchronously with the pulsesφ_(v2).

In FIG. 2B, by properly setting the timings for the drive pulses φ_(v1)and φ_(v2), the waveforms of the scan pulses φ₁ to φ_(n) can be madeapproach a square shape.

FIG. 3 is a partial circuit diagram of the second embodiment of theinvention. FIG. 4 is a voltage waveform diagram for explaining theoperation thereof.

In this embodiment, first, the transistor M₁ is turned on and thepotential V(A) rises by the start pulse P_(s) and drive pulse φ_(v1).Thus, the transistors Mhd 2and M₃ exhibit a certain conductance.

Subsequently, since the drive pulse φv1 falls, an output of an inverter501 rises. Consequently, a voltage is applied to a capacitor C_(p)through the transistor M₃ and the potential V(A) further rises by thebootstrap effect.

Therefore, if such a change in the potential V(A) is used as a scanpulse φ₁, the scan pulse at a high voltage can be derived in a mannersimilar to the first embodiment. In a manner similar to the above, scanpulses φ₂ to φ_(n) at a high voltage level can be successively outputsynchronously with the drive pulses φ_(v1) and φ_(v2).

Therefore, even when the interlacing circuit shown in FIG. 1 isprovided, the voltage drop can be sufficiently compensated and the highlevel drive voltage can be transferred to the horizontal lines HDL.

FIG. 5 is a schematic circuit diagram of a drive section using the scancircuit of the embodiment. FIG. 6 is a timing chart for explaining theoperation thereof.

As shown in FIG. 5, the image pickup device comprises photoelectricconverting cells C₁₁, C₁₂, . . . and the like which are arranged like anarea and driven every row by the horizontal lines HDL₁, HDL₂, HDL₃, . .. The photoelectric conversion signals are read out through the verticallines and transistors Q₁ and Q₂.

In this embodiment, gate electrodes of three transistors Q_(v1) toQ_(v3) are connected to output terminals of a scan circuit 101,respectively.

Each transistor Q_(v1) transfers a drive voltage V_(r1) to thehorizontal lines HDL₁, HDL₃, HDL₅, . . . Each transistor Q_(v2)transfers a drive voltage V_(r2) to the horizontal lines HDL₂, HDL₄,HDL₆, . . . Each transistor Q_(v3) transfers a drive voltage V_(r3) tothe HDL₃, HDL₅, HDL₇, . . .

In such a circuit arrangement, the scan circuit 101 sequentially outputsthe scan pulses φ₁, φ₂, . . . in response to pulses φ_(v1) and φ_(v2).Therefore, by applying the drive voltages V_(r1) to V_(r3) by a propercombination, the image pickup device can be scanned in a desired mode.

For example, as shown in FIG. 6, by applying the drive voltage V_(r1)and V_(r2) in the odd number fields, the horizontal lines HDL₁ and HDL₂,and HDL₃ and HDL₄, . . . are driven and by applying the drive voltageV_(r2) and V_(r3) in the even number fields, the HDL₂ and HDL₃, and HDL₄and HDL₅, . . . are driven. In this manner, the interlacing scan of thetwo line driving type can be accomplished.

On the other hand, if the drive voltages V_(r1) and V_(r2) and the drivevoltages V_(r2) and V_(r3) are applied at different timings which aredeviated from each other, the vertical line of the image pickup devicecan be also set to a single vertical line.

Even when such a vertical buffer circuit is provided, since the outputof the scan circuit 101 according to the embodiment is set to the highvoltage level, the transistors Q_(v1) to Q_(v3) can be set to enoughhigh conductances. The drive voltages V_(r1) to V_(r3) can betransferred to the horizontal lines HDL without reducing the drivevoltages V_(r1) to V_(r3).

FIG. 7 is a schematic circuit diagram of another example of a drivesection using the scan circuit of the embodiment. FIG. 8 is a timingchart for explaining the operation thereof.

In this manner, by providing the transistors Q_(v1) to Q_(v4) at therespective output terminals of the scan circuit 101 and by combining thedrive voltages V_(r1) to V_(r4) as shown in the timing chart, theinterlacing scan of the three-line driving type can be alsoaccomplished.

A practical example of a solid state image pickup apparatus using theembodiment will now be explained.

FIG. 9 is a schematic cross sectional view of an example ofphotoelectric converting cells which are used in the solid state imagepickup apparatus.

In the diagram, an n⁻ layer 202 serving as a collector region is formedon an n type silicon substrate 201 by the epitaxial growth. A p baseregion 203 is formed in the n⁻ layer 202. An n⁺ emitter region 204 isfurther formed in the p base region 203. In this manner, a bipolartransistor is constituted.

The p base region 203 is two-dimensionally arranged. The cells in thehorizontal direction are separated from the cells in the verticaldirection by a device separating region. Although not shown, the deviceseparating region comprises an oxide film formed by the LOCOS oxidationand an n⁺ region formed under the oxide film.

On the other hand, a gate electrode 208 is formed between horizontallyneighboring p base regions 203 through an oxide film 207. Therefore, a pchannel MOS transistor in which the adjacent p base regions 203 are usedas source and drain regions is constituted.

This MOS transistor is the normally OFF type and is set to the OFF statewhen the potential of the gate electrode 208 is the earth potential orpositive potential. Therefore, the p base regions 203 between theadjacent cells are electrically isolated. On the contrary, when thepotential of the gate electrode 208 is a negative potential whichexceeds a threshold value potential V_(th), the MOS transistor is set tothe ON state, so that the p base regions 203 of the respective cells aremutually made conductive.

The gate electrodes 208 are commonly connected to the drive line everyrow in the horizontal direction. Further, capacitors 209 to control thepotentials of the p base regions 203 are also similarly connected to thedrive line. The drive line extends in the horizontal direction on theoxide film serving as the device separating region.

Further, after a transparent insulative layer 211 was formed, an emitterelectrode 212 is formed. The emitter electrodes 212 are connected to avertical line 213 every column. A collector electrode 214 is formed onthe back surface of the substrate 201 through an ohmic contact layer.

FIG. 10A is an equivalent circuit diagram of the photoelectricconverting cell. FIG. 10B is a voltage waveform diagram for explainingthe operation thereof.

It is now assumed that carriers (in this case, holes) as much as theincident light amount are accumulated in the p base region 203. It isalso assumed that a negative voltage V_(c) is applied to a terminal of atransistor Q_(c) and a positive voltage is applied to the collectorelectrode 214.

In this state, pulses φ_(d) of a positive voltage are applied to a driveline 210 for only a period of time T_(rd). Thus, the potential of the pbase region 203 rises through a capacitor C_(ox) and the signal is readout to the emitter electrode 212 as mentioned above.

Subsequently, pulses φ_(d) of a negative voltage are applied to thedrive line 210 for only a period of time T_(rh). Thus, the p channel MOStransistor Q_(c) is turned on and the base potential is reset to thevoltage V_(c) and the refreshing operation is completely performed. Onthe other hand, by setting a pulse φ_(r) to the high level, thetransistor Q_(r) is turned on, thereby resetting the vertical line 213.

As already mentioned above, as the refreshing operation, after the MOStransistor Q_(c) was turned on, the pulse φ_(d) of a positive voltagecan be also applied while the emitter electrode 212 is grounded. In thiscase, there is no need to set the voltage V_(c) to a negative voltagebut can be set to the earth voltage or positive voltage.

After completion of the foregoing refreshing operation, the accumulatingoperation is started. The similar operations are repeated hereinafter.

FIG. 11 is a schematic circuit diagram of an image pickup apparatususing the foregoing photoelectric converting cells.

In this apparatus, m × n photoelectric converting cells are arrangedlike an area.

In the cells C_(1l) to C_(1n), C_(2l) to C_(2n), . . . on the horizontallines, the gate electrodes 208 of the MOS transistor Q_(c) are commonlyconnected to the drive lines HDL_(l) to HDL_(m), respectively.

The drive lines HDL_(l) to HDL_(m) are connected to a vertical buffercircuit 301. The scan pulses φ_(l) to φ_(m) are input to the verticalbuffer circuit 301 from the vertical scan circuit 101 as the embodiment.

The MOS transistors Q_(c) in each of which the p base regions 203 ineach cell are used as source and drain regions are serially connectedevery horizontal line. The p regions to form the MOS transistor Q_(c)are respectively formed in the cells C_(1l) to C_(ml) arranged at theedge line. On the other hand, MOS transistors Q_(xl) to Q_(xm) arerespectively serially connected to the cells C_(1n) to C_(mn). Aconstant voltage V_(c) is applied to both ends.

The emitter electrodes in the cells C₁₁ to C_(m1), C₁₂ to C_(m2), . . .in the vertical direction are commonly connected to vertical linesV_(Ll) to V_(Ln), respectively. The vertical lines are grounded throughreset transistors Q_(rl) to Q_(rn). A reset pulse φ_(r) is commonlyinput to the gate electrodes of the transistors Q_(rl) to Q_(rn).

The vertical lines VL_(l) to VL_(n) are connected to capacitors C₁ andC₂ through transistors Q_(t1) and Q_(t2), respectively. The pulsesφ_(t1) and φ_(t2) are input to the gate electrodes of the transistorsQ_(t1) and Q_(t2).

Further, the capacitors C₁ and C₂ are connected to signal lines 303 and304 through the transistors Q₁ and Q₂, respectively. Scan pulses φ_(ll)to φ_(nl) of a horizontal scan circuit 302 are input to the gateelectrodes of the transistors Q₁ and Q₂, respectively.

Various kinds of pulses φ, voltages V, and the like to drive the imagepickup apparatus are supplied from a driver 305. The driver 305 iscontrolled by a controller 306.

FIG. 12 is a timing chart for schematically explaining the operation ofthe image pickup apparatus.

In the odd number fields F_(o), when the pulses φ_(v1) and φ_(v2) areinput to the vertical scan circuit 101, the scan pulse φ₁ rises. Thescan pulse φ₁ is set to the high voltage since it uses the bootstrapeffect as mentioned above.

Thus, the vertical buffer circuit 301 outputs input voltages V_(r1) andV_(r2) to the horizontal lines HDL₁ and HDL₂, respectively.

Simultaneously with the rising of the pulse φ_(v2), the pulses φ_(t1)and φ_(r) rise and the transfer transistor Q_(t1) and reset transistorQ_(r) are turned on, thereby clearing the vertical lines VL andcapacitor C₁.

Subsequently, after the reset transistor Q_(r) was turned off, the inputvoltage V_(r1) is set to a positive voltage and the reading operationsof the cells C_(1l) to C_(1n) on the horizontal line HDL₁ are executed.The readout signals are stored into the capacitor C₁ through thetransfer transistor Q_(t1), respectively.

Next, when the pulses φ_(t2) and φ_(r) rise, the transfer transistorQ_(t2) and reset transistor Q_(r) are turned on, thereby clearing thecapacitor C₂ and vertical lines VL.

Subsequently, the input V_(r2) is set to a positive voltage and thereading operations of the cells C₂₁ to C_(2n) on the horizontal lineHDL₂ are executed. The readout signals are stored into the capacitor C₂through the transfer transistor Q_(t2).

The foregoing operations are performed within a horizontal blankingperiod HBLK. Next, the sensor signals of the first and second rows whichwere accumulated in the capacitors C₁ and C₂ within the effectivehorizontal period are scanned and output.

Namely, the transistors Q₁ and Q₂ are sequentially turned on by the scanpulses φ_(l1) to φ_(n1) which are successively output from thehorizontal scan circuit 302. The signals stored in the capacitors C₁ andC₂ are read out and output to the signal lines 303 and 304.

In parallel with those operations, the pulse φ_(r) rises and thetransistor Q_(r) is turned on, thereby grounding the vertical lines VL.On the other hand, the input voltages V_(r1) and V_(r2) are set to anegative voltage, thereby refreshing the cells of the first and secondrows. That is, the MOS transistor Q_(c) of each cell are turned on andeach base potential is set to a constant value.

Next, the input voltages V_(r1) and V_(r2) are set to a positivevoltage, thereby refreshing the base regions 203 which were reset to aconstant potential. In other words, since the emitter electrodes of thecells are grounded through the vertical lines VL, when a positivevoltage is applied to capacitors C_(ox), the circuit between the baseand emitter is forwardly biased, so that the carriers accumulated in thebase region 203 are extinguished in a manner similar to the readingoperations.

After completion of the refreshing operation in this manner, the cellsof the first and second rows start the accumulating operation.

In a manner similar to the above, the reading and refreshing operationsof the third and fourth rows, the fifth and sixth rows, . . . in the oddnumber fields F_(o) are sequentially executed by the pulses φ_(v1) andφ_(v2).

In the even number fields F_(e), the reading and refreshing operationsof the second and third rows, the fourth and fifth rows, . . . aresuccessively performed by the input V_(r2) and V_(r3).

By using the scan circuit 101 according to the embodiment of theinvention in the drive section of the image pickup apparatus, the goodpicture quality can be derived without providing any special voltagelevel compensating circuit or the like.

As explained in detail above, according to the scan circuit of theinvention, the scan pulse can be set to a high voltage level by use ofthe bootstrap effect. Thus, even when the interlacing circuit or thelike is provided, the scan can be performed by an enough high voltage.

Thus, there is no need to compensate the output level by adding thebootstrap capacitance as in the conventional apparatus. The circuitconstitution is simplified and the area of the elements can be easilyreduced.

According to the drive circuit of the invention, since the drive signalsare supplied to the drive lines in a desired mode on the basis of thescan output of the scan circuit and a desired combination of the drivesignals, even when a plurality of drive lines are scanned, they can beindependently driven. Various kinds of driving modes such as interlacingscan, non-interlacing scan, and the like of a plurality of lines can beeasily performed.

What is claimed is:
 1. A solid state image pickup apparatuscomprising:a) a plurality of photosensitive cells arranged in a row andcolumn array; b) a selecting line to select the photosensitive cells ona predetermined row from among said plurality of photosensitive cells;c) scanning means for supplying an address signal to said selectingline, said scanning means having a plurality of stages and outputsignals being sequentially output one by one from said stages andcomprising at least two bootstrap means connected with each other to mixdrive pulses whose voltages are raised by said at least two bootstrapmeans, respectively, at a junction of said at least two bootstrap meansto provide the mixed drive pulse as the address signal; d) switchingmeans each including three or more switching elements which areconnected to outputs of each stage of the scanning means and arecontrolled, and each of the three or more switching elements of eachswitching means being connected to a different selecting line,respectively; e) another control means different from said scanningmeans, said another control means being provided to control theoperations of said three or more switching elements.
 2. An apparatusaccording to claim 1, wherein the selecting lines controlled by saidthree or more switching elements connected to a predetermined stage ofsaid scanning means are in overlapping relationship with the selectinglines controlled by the three or more switching elements connected toanother stage of said scanning means adjacent to said predeterminedstage.
 3. An apparatus according to claim 1, wherein said anothercontrol means turns on at least two of said switching elements for oneimage pickup.
 4. An apparatus according to claim 1, wherein saidscanning means includes a vertical scanning circuit.
 5. An image pickupdevice comprising:first scanning means for selecting a plurality ofphotosensitive cells arranged in a row and column array, by row tooutput a scanning pulse; and second scanning means for selecting saidplurality of photosensitive cells by column to output a scanning pulse;means for generating drive pulses; wherein said first scanning meanscomprises at least two bootstrap means connected with each other to mixdrive pulses whose voltages are raised by said at least two bootstrapmeans, respectively, at a junction of said two bootstrap means toprovide a mixed drive pulse as the scanning pulse.
 6. A device accordingto claim 5, wherein said first scanning means includes means forgenerating a vertical scanning pulse and said second scanning meansincludes means for generating a horizontal scanning pulse.
 7. A deviceaccording to claim 5, wherein the scanning pulse output from said firstscanning means is distributed to photosensitive elements of at least tworows, and said at least two rows partially overlap two rows ofphotosensitive elements to which an another scanning pulse isdistributed.
 8. A device according to claim 5, wherein the scanningpulse is distributed to at least two rows of photosensitive elements,and signals respectively output from the photosensitive elements of saidat least two rows are output through different output linesrespectively.
 9. A device according to claim 8, wherein said signalsoutput through the output lines are synchronized with each other.